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| Semiconductor MSM56V16160F 2-Bank 524,288 Word 16 Bit SYNCHRONOUS DYNAMIC RAM This version : Sep.1999 DESCRIPTION The MSM56V16160F is a 2-Bank 524,288-word 16 bit Synchronous dynamic RAM, fabricated in OKI's CMOS silicon-gate process technology. The device operates at 3.3V. The inputs and outputs are LVTTL compatible. FEATURES * * * * * * * Silicon gate , quadruple polysilicon CMOS , 1-transistor memory cell 2-bank 524,288-word 16bit configuration 3.3V power supply 0.3V tolerance Input Output Refresh : LVTTL compatible : LVTTL compatible : 4096 cycles/64 ms Programmable data transfer mode - CAS Latency (1,2,3) - Burst Length (1,2,4,8,Full page) - Data scramble (sequential , interleave) * * CBR auto-refresh, Self-refresh capability Package: 50-pin 400mil plastic TSOP (Type II) (TSOPII50-P-400-0.80-K) (Product : MSM56V16160F-xxTS-K) xx : indicates speed rank. PRODUCT FAMILY Family MSM56V16160F-8 MSM56V16160F-10 Max. Frequency 125MHz 100MHz Access Time (Max.) tAC2 9ns 9ns tAC3 6ns 9ns 1/30 MSM56V16160F PIN CONFIGRATION (TOP VIEW) VCC DQ1 DQ2 VSSQ 1 2 3 4 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS DQ16 DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 DQ9 VCCQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 VSS DQ3 5 DQ4 6 VCCQ 7 DQ5 8 DQ6 9 VSSQ 10 DQ7 11 DQ8 12 VCCQ 13 LDQM 14 WE 15 CAS 16 RAS 17 CS 18 A11 19 A10 20 A0 21 A1 22 A2 23 A3 24 VCC 25 50-Pin Plastic TSOP (II) (K Type) Pin Name CLK CS CKE A0-A10 A11 RAS CAS WE Function System Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Pin Name UDQM, LDQM DQi VCC VSS VCCQ VSSQ NC Function Data Input/Output Mask Data Input/Output Power Supply (3.3V) Ground (0V) Data Output Power Supply (3.3V) Data Output Ground (0V) No Connection Note: The same power supply voltage must be provided to every VCC pin and VCCQ pin. The same GND voltage level must be provided to every VSS pin and VSSQ pin. 2/30 MSM56V16160F PIN DESCRIPTION CLK CS Fetches all inputs at the "H" edge. Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE, UDQM and LDQM. Masks system clock to deactivate the subsequent CLK operation. If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is deactivated. CKE should be asserted at least one cycle prior to a new command. Row & column multiplexed. Row address : RA0 - RA10 Column Address : CA0 - CA7 Slects bank to be activated during row address latch time and selects bank for precharge and read/write during column address latch time. A11="L" : Bank A, A11="H" : Bank B Functionality depends on the combination. For details, see the function truth table. Masks the read data of two clocks later when UDQM and LDQM are set "H" at the "H" edge of the clock signal. Masks the write data of the same clock when UDQM and LDQM are set "H" at the "H" edge of the clock signal. UDQM controls upper byte and LDQM controls lower byte. Data inputs/outputs are multiplexed on the same pin. CKE Address A11 RAS CAS WE UDQM, LDQM DQi 3/30 MSM56V16160F BLOCK DIAGRAM CKE CLK CS RAS CAS WE UDQM LDQM Latency & Burst Controller I/O Controller Timing Register Programing Register Bank Controller A11 Internal Col. Address Counter A0 - A11 Input Data Register 16 88 Column Address Buffers 8 Column Decoders Input Buffers 16 Sense Amplifiers Internal Row Address Counter 16 Read Data Register 16 Output Buffers 16 DQ1 - DQ16 Row Decoders Word Drivers 8Mb Memory Cells 12 Row Address Buffers 12 Row Decoders Word Drivers 8Mb Memory Cells Sense Amplifiers Column Decoders 4/30 MSM56V16160F ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (Voltages referenced to VSS) Parameter Voltage on Any Pin Relative to VSS VCC Supply Voltage Storage Temperature Power Dissipation Short Circuit Current Operating Temperature Symbol VIN, VOUT VCC, VCCQ Tstg PD* IOS Topr *: Ta = 25C Rating -0.5 to VCC + 0.5 -0.5 to 4.6 -55 to 150 600 50 0 to 70 Unit V V C mW mA C Recommended Operating Conditions (Voltages referenced to VSS = 0V) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC, VCCQ VIH VIL Min. 3.0 2.0 -0.3 Typ. 3.3 3/4 3/4 Max. 3.6 VCC + 0.2 0.8 Unit V V V Capacitance (VBIAS = 1.4V, Ta = 25C, f = 1MHz) Parameter Input Capacitance (CLK) Input Capacitance (RAS, CAS, WE, CS, CKE, UDQM, LDQM, A0-A11) Input/Output Capacitance (DQ1-DQ16) Symbol CCLK CIN COUT Min. 2.5 2.5 4 Max. 4 5 6.5 Unit pF pF pF 5/30 MSM56V16160F DC Characteristics Condition Parameter Output High Voltage Output Low Voltage Input Leakage Current Input Leakage Current Symbol Bank VOH VOL ILI ILO 3/4 3/4 3/4 3/4 One Bank Active CKE 3/4 3/4 3/4 3/4 Others IOH = -2.0mA IOL = 2.0mA 3/4 3/4 MSM56V16160 F-8 Min 2.4 3/4 -10 -10 Max 3/4 0.4 10 10 F-10 Min 2.4 3/4 -10 -10 Max 3/4 0.4 10 10 V V A A Unit Note ICC1 Average power supply current (Operating) tCC=min. CKEVIH tRC=min. No Burst 3/4 80 3/4 70 mA 1,2 ICC1D tCC=min. t =min. Both Banks CKEVIH RC Active tRRD=min. No Burst Both Banks CKEVIH tCC=min. Precharge Both Banks CKEVIL tCC=min. Active One Bank Active 3/4 115 3/4 95 mA 1,2 Power supply current (Standby) Average power supply current (Clock Suspension) Average power supply current (Active Standby ) Power supply current (Burst) Power supply current (Auto-Refresh) Average power supply current (Self-Refresh) Average power supply current (Power Down) ICC2 3/4 35 3/4 30 mA 3 ICC3S 3/4 3 3/4 3 mA 2 ICC3 CKEVIH tCC=min. 3/4 40 3/4 35 mA 3 ICC4 Both Banks CKEVIH tCC=min. Active One Bank Active CKEVIH tCC=min. tRC=min. 3/4 125 3/4 100 mA 1,2 ICC5 3/4 80 3/4 70 mA 2 ICC6 Both Banks CKEVIL tCC=min. Precharge Both Banks CKEVIL tCC=min. Precharge 3/4 2 3/4 2 mA ICC7 3/4 2 3/4 2 mA Notes: 1. 2. 3. Measured with outputs open. The address and data can be changed once or left unchanged during one cycle. The address and data can be changed once or left unchanged during two cycles. 6/30 MSM56V16160F Mode Set Address Keys CAS Latency A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CL Reserved 1 2 3 Reserved Reserved Reserved Reserved Burst Type A3 0 1 BT Sequential Interleave A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 Burst Length A0 0 1 0 1 0 1 0 1 BT = 0 1 2 4 8 Reserved Reserved Reserved Full Page BT = 1 1 2 4 8 Reserved Reserved Reserved Reserved Notes: A7, A8, A9, A10 and A11 should stay "L" during mode set cycle. POWER ON SEQUENCE 1. 2. 3. 4. 5. With inputs in NOP state, turn on the power supply and start the system clock. After the VCC voltage has reached the specified level, pause for 200ms or more with the input kept in NOP state. Issue the precharge all bank command. Apply a CBR auto-refresh eight or more times. Enter the mode register setting command. 7/30 MSM56V16160F AC Characteristic (1/2) Note 1,2 MSM56V16160 Parameter Symbol Min. CL = 3 Clock Cycles Time CL = 2 CL = 1 CL = 3 Access Time from Clock CL = 2 CL = 1 Clock High Pulse Time Clock Low Pulse Time Input Setup Time Input Hold Time Output Low Impedance Time from Clock Output High Impedance Time from Clock Output Hold from Clock RAS Cycle Time RAS Precharge Time RAS Active Time RAS to CAS Delay Time Write Recovery Time RAS to RAS Bank Active Delay Time Refresh Time Power-down Exit setup Time Input Level Transition Time CAS to CAS Delay Time(Min.) Clock Disable Time from CKE Data Output High Impedance Time from UDQM, LDQM Data Input Mask Time from UDQM, LDQM Data Input Mask Time from Write Command tCH tCL tSI tHI tOLZ tOHZ tOH tRC tRP tRAS tRCD tWR tRRD tREF tPDE tT lCCD lCKE lDOZ lDOD lDWD tAC tCC 8 12 24 3/4 3/4 3/4 3 3 2 1 3 3/4 3 70 20 48 20 8 20 3/4 tSI+1CLK 3/4 1 1 2 0 0 F-8 Max. 3/4 3/4 3/4 6 9 22 3/4 3/4 3/4 3/4 3/4 8 3/4 3/4 3/4 10 5 F-10 Min. 10 15 30 3/4 3/4 3/4 3 3 3 1 3 3/4 3 90 30 60 30 15 20 3/4 tSI+1CLK 3/4 1 1 2 0 0 8 3/4 3/4 3/4 10 5 Unit Max. 3/4 3/4 3/4 9 9 27 3/4 3/4 3/4 3/4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns Cycle Cycle Cycle Cycle Cycle Note 3,4 3,4 3,4 4 4 3 3/4 3/4 3/4 64 3/4 3 3/4 3/4 3/4 64 3/4 3 8/30 MSM56V16160F AC Characteristic (2/2) Note 1,2 MSM56V16160 Parameter Symbol Min. Data Output High Impedance Time from Precharge Command Active Command Input Time from Mode Register Set Command Input (Min.) Write Command Input Time from Output lROH lMRD lOWD CL 3 F-8 Max. Min. CL 3 F-10 Max. Cycle Cycle Unit Note 2 2 Cycle Notes: 1) 2) 3) AC measurements assume that tT = 1ns. The reference level for timing of input signals is 1.4V. Output load. Z=50W Output 50pF (External Load) 4) 5) The access time is defined at 1.5V. If tT is longer than 1ns, then the reference level for timing of input signals is VIH and VIL. 9/30 MSM56V16160F TIMING WAVEFORM * Read & Write Cycle (Same Bank) @CAS Latency=2, Burst Length=4 = = 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tRC CKE CS tRP RAS tRCD CAS ADDR Ra C a0 Rb C b0 A11 A10 Ra Rb tOH DQ Q a0 Q a1 Q a2 Q a3 D b0 D b1 D b2 D b3 tAC WE UDQM, LDQM Row Active Read Command tOHZ tWR Precharge Command Row Active Write Command Precharge Command 10/30 MSM56V16160F * Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency=2, Burst Length=4 = = tCH 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tCC CKE tCL High CS tHI RAS tSI tSI CAS tHI ICCD tSI ADDR Ra tSI Ca tSI Cb Cc tHI A11 BS BS tHI BS BS BS A10 Ra tAC DQ Qa tOHZ Db tHI Qc tOLZ tOH lOWD WE tSI tHI tSI UDQM, LDQM Row Active Read Command Write Command Precharge Command Read Command 11/30 MSM56V16160F *Notes : 1. When CS is set "High" at a clock transition from "Low" to "High", all inputs except CKE, UDQM and LDQM are invalid. 2. When issuing an active, read or write command, the bank is selected by A11. A11 0 1 Active, read or write Bank A Bank B 3. The auto precharge function is enabled or disabled by the A10 input when the read or write command is issued. A10 0 1 0 1 A11 0 0 1 1 Operation After the end of burst, bank A holds the idle status. After the end of burst, bank A is precharged automatically. After the end of burst, bank B holds the idle status. After the end of burst, bank B is precharged automatically. 4. When issuing a precharge command, the bank to be precharged is selected by the A10 and A11 inputs. A10 0 0 1 A11 0 1 X Operation Bank A is precharged. Bank B is precharged. Both banks A and B are precharged. 5. The input data and the write command are latched by the same clock (Write latency = 0). 6. The output is forced to high impedance by (1CLK+tOHZ) after UDQM, LDQM entry. 12/30 MSM56V16160F * Page Read & Write Cycle (Same Bank) @CAS Latency=2, Burst Length=4 = = 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE High CS Bank A Active RAS CAS ICCD ADDR C a0 C b0 C c0 C d0 A11 A10 DQ Q a0 Q a1 Q b0 Q b1 D c0 D c1 D d0 lOWD WE UDQM, LDQM Read Command Read Command tWR *Note 2 *Note 1 Write Command Precharge Command Write Command *Notes: 1. To write data before a burst read ends, UDQM and LDQM should be asserted three cycles prior to the write command to avoid bus contention. 2. To assert row precharge before a burst write ends, wait tWR after the last write data input. Input data during the precharge input cycle will be masked internally. 13/30 MSM56V16160F * Read & Write Cycle with Auto Precharge @ Burst Length=4 = 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE High CS RAS tRRD CAS ADDR Ra Rb Ca Cb A11 A10 Ra Rb WE CAS Latency=1 DQ UDQM, LDQM CAS Latency=2 DQ UDQM, LDQM CAS Latency=3 DQ UDQM, LDQM Row Active (A-Bank) Row Active (B-Bank) A Bank Read with Auto Precharge Q a0 Q a1 Q a2 Q a3 D b0 D b1 D b2 D b3 A-Bank Precharge Start Q a0 Q a1 Q a2 Q a3 D b0 D b1 D b2 D b3 A-Bank Precharge Start Q a0 Q a1 Q a2 Q a3 D b0 D b1 D b2 D b3 A-Bank Precharge Start tWR B Bank Write with Auto Precharge B Bank Precharge Start Point 14/30 MSM56V16160F * Bank Interleave Random Row Read Cycle @CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE High CS tRC RAS tRRD CAS ADDR R Aa C Aa R Bb C Bb R Ac C Ac A11 A10 R Aa R Bb R Ac DQ Q Aa0 Q Aa1 Q Aa2 Q Aa3 Q Bb1 Q Bb2 Q Bb3 Q Bb4 Q Ac0 Q Ac1 Q Ac2 Q Ac3 WE UDQM, LDQM Row Active (A-Bank) Read Command (A-Bank) Row Active (B-Bank) Read Command (B-Bank) Row Active (A-Bank) Read Command (A-Bank) Precharge Command (A-Bank) Precharge Command (B-Bank) 15/30 MSM56V16160F * Bank Interleave Random Row Write Cycle @CAS Latency = 2, Burst Length =4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE High CS RAS CAS ADDR R Aa C Aa R Bb C Bb R Ac C Ac A11 A10 R Aa R Bb R Ac DQ D Aa0 D Aa1 D Aa2 D Aa3 D Bb0 D Bb1 D Bb2 D Bb3 D Ac0 D Ac1 WE UDQM, LDQM Row Active (A-Bank) Row Active (B-Bank) Write Command (A-Bank) Precharge Command Write Command (A-Bank) (B-Bank) Row Active (A-Bank) Write Command (A-Bank) Precharge Command (A-Bank) Precharge Command (B-Bank) 16/30 MSM56V16160F * Bank Interleave Page Read Cycle @CAS Latency = 2, Burst Length =4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE *Note 1 High CS RAS CAS ADDR R Aa C Aa R Bb C Bb C Ac C Bd C Ae A11 A10 R Aa R Bb DQ Q Aa0 Q Aa1 Q Aa2 Q Aa3 Q Bb0 Q Bb1 Q Bb2 Q Bb3 Q Ac0 Q Ac1 Q Bd0 Q Bd1 Q Ae0 Q Ae1 IROH WE UDQM, LDQM Row Active (A-Bank) Read Command (A-Bank) Row Active (B-Bank) Read Command (B-Bank) Read Command (B-Bank) Read Command (A-Bank) Read Command (A-Bank) Precharge Command (A-Bank) *Note: 1. CS is ignored when RAS, CAS and WE are high at the same cycle. 17/30 MSM56V16160F * Bank Interleave Page Write Cycle @CAS Latency = 2, Burst Length=4 = 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE High CS RAS CAS ADDR R Aa C Aa R Bb C Bb C Ac C Bd A11 A10 R Aa R Ab DQ D Aa0 D Aa1 D Aa2 D Aa3 D Bb0 D Bb1 D Bb2 D Bb3 D Ac0 D Ac1 D Bd0 WE UDQM, LDQM Row Active Row Active (A-Bank) Write Command (B-Bank) Write Command (B-Bank) (A-Bank) Write Command Write Command (B-Bank) Precharge Command (A-Bank) (Both Bank) 18/30 MSM56V16160F * Bank Interleave Random Row Read/Write Cycle @CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE High CS RAS CAS ADDR R Aa C Aa R Bb C Bb R Ac C Ac A11 A10 R Aa R Bb R Ac DQ Q Aa0 Q Aa1 Q Aa2 Q Aa3 Q Bb0 Q Bb1 Q Bb2 Q Bb3 Q Ac0 Q Ac1 Q Ac2 Q Ac3 WE UDQM, LDQM Row Active (A-Bank) Read Command (A-Bank) Row Active (B-Bank) Precharge Command (A-Bank) Write Command (B-Bank) Read Command (A-Bank) Row Active (A-Bank) 19/30 MSM56V16160F * Bank Interleave Page Read/Write Cycle @CAS Latency = 2, Burst Length =4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE High CS RAS CAS ADDR C Aa0 C Bb0 C Ac0 A11 A10 DQ Q Aa0 Q Aa1 Q Aa2 Q Aa3 D Bb0 D Bb1 D Bb2 D Bb3 Q Ac0 Q Ac1 Q Ac2 Q Ac3 WE UDQM, LDQM Read Command (A-Bank) Write Command (B-Bank) Read Command (A-Bank) 20/30 MSM56V16160F * Clock Suspension & DQM Operation Cycle @CAS Latency = 2, Burst Length =4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK *Note 1 *Note 1 CKE CS RAS CAS ADDR Ra Ca Cb Cc A11 A10 Ra DQ0-7 *Note 4 Q a0 Q a1 Q a2 Q b0 Q b1 D c0 *Note 3 D c0 D c1 D c2 tOHZ Q a0 *Note 2 Q a2 Q a3 tOHZ Q b0 Q b1 DQ8-15 WE UDQM *Note 4 LDQM Row Active Read DQM CLOCK Suspension Read DQM Read Command Read DQM Write DQM CLOCK Suspension Write DQM Read Command Write Command *Notes: 1. 2. 3. 4. When Clock Suspension is asserted, the next clock cycle is ignored. When LDQM and UDQM are asserted, the read data after two clock cycles is masked. When LDQM and UDQM are asserted, the write data in the same clock cycle is masked. When LDQM is set High, the input/output data of DQ0-7 is masked. When UDQM is set High, the input/output data of DQ8-15 is masked. 21/30 MSM56V16160F * Read to Write Cycle (Same Bank) @CAS Latency = 2, Burst Length =4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS *Note 1 RAS tRCD CAS ADDR Ra C a0 C b0 A11 A10 Ra DQ D a0 D b0 D b1 D b2 D b3 tWR WE UDQM, LDQM Row Active Read Command Write Command Precharge Command *Note: 1. In Case CAS latency is 3, READ can be interrupted by WRITE. The minimum command interval is [burst length + 1] cycles. UDQM and LDQM must be high at least 3 clocks prior to the write command. 22/30 MSM56V16160F * Read Interruption by Precharge Command @Burst Length =8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR Ra Ca A11 A10 Ra WE CAS Latency=1 DQ UDQM, LDQM CAS Latency=2 DQ UDQM, LDQM CAS Latency=3 DQ UDQM, LDQM Row Active Read Command Precharge Command *Note 1 Q a0 Q a1 Q a2 Q a3 Q a4 Q a5 lROH *Note 2 Q a0 Q a1 Q a2 Q a3 Q a4 Q a5 lROH *Note 3 Q a0 Q a1 Q a2 Q a3 Q a4 Q a5 lROH *Notes: 1. 2. 3. When the CAS latency = 1, and if row precharge is asserted before a burst read ends, then the read data will not output after the next clock cycle of the precharge command. When the CAS latency = 2, and if row precharge is asserted before burst read ends, then the read data will not output after the second clock cycle of the precharge command. When the CAS latency = 3, and if row precharge is asserted before burst read ends, then the read data will not output after the second clock cycle of the precharge command. 23/30 MSM56V16160F * Burst Stop Command @Burst Length =8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE High CS RAS CAS ADDR Ca Cb A11 A10 WE CAS Latency=1 DQ UDQM, LDQM CAS Latency=2 DQ UDQM, LDQM CAS Latency=3 DQ UDQM, LDQM Read Command Burst Stop Command Write Command Burst Stop Command Q a0 Q a1 Q a2 Q a3 Q a4 Q b0 Q b1 Q b2 Q b3 Q b4 Q a0 Q a1 Q a2 Q a3 Q a4 Q b0 Q b1 Q b2 Q b3 Q b4 Q a0 Q a1 Q a2 Q a3 Q a4 Q b0 Q b1 Q b2 Q b3 Q b4 24/30 MSM56V16160F * Power Down Mode @CAS Latency = 2, Burst Length =4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tSI CKE tPDE *Note 2 *Note 1 tSI tSI tREF (min.) CS RAS CAS ADDR Ra Ca A11 A10 Ra DQ WE UDQM, LDQM Power-down Entry Power-down Exit Row Active Clock Suspension Entry Q a0 Q a1 Q a2 Read Command Clock Suspension Exit Precharge Command *Notes: 1. When both banks are in precharge state, and if CKE is set low, then the MSM56V16160F enters power-down mode and maintains the mode while CKE is low. 2. To release the circuit from power-down mode, CKE has to be set high for longer than t PDE (tSI + 1CLK). 25/30 MSM56V16160F * Self Refresh Cycle 0 1 2 CLK tRC CKE tSI CS RAS CAS ADDR Ra A11 BS A10 Ra DQ WE UDQM, LDQM Self Refresh Entry Hi - Z Self Refresh Exit Row Active 26/30 MSM56V16160F * Mode Register Set Cycle 0 1 2 3 4 5 6 * 0 Auto Refresh Cycle 1 2 3 4 5 6 7 8 9 10 11 CLK CKE High High CS lMRD RAS tRC CAS ADDR DQ Key Ra Hi - Z Hi - Z WE UDQM, LDQM MRS New Command Auto Refresh Auto Refresh 27/30 MSM56V16160F FUNCTION TRUTH TABLE (Table 1) (1/2) Current State Idle 1 CS H L L L L L L L H L L L L L L H L L L L L L L H L L L L L L L H L L L L L L H L L L L L L RAS X H H H L L L L X H H H L L L X H H H H L L L X H H H H L L L X H H H H L L X H H H H L L CAS X H H L H H L L X H L L H H L X H H L L H H L X H H L L H H L X H H L L H L X H H L L H L WE X H L X H L H L X X H L H L X X H L H L H L X X H L H L H L X X H L H L X X X H L H L X X BA X X BA BA BA BA X L X X BA BA BA BA X X X X BA BA BA BA X X X X BA BA BA BA X X X BA BA X BA X X X BA BA X BA X ADDR X X X CA RA A10 X OP Code X X CA, A10 CA, A10 RA A10 X X X X CA, A10 CA, A10 RA A10 X X X X CA, A10 CA, A10 RA A10 X X X X CA, A10 X RA, A10 X X X X CA, A10 X RA, A10 X NOP NOP ILLEGAL 2 ILLEGAL 2 Row Active NOP 4 Action Auto-Refresh or Self-Refresh 5 Mode Register Write NOP NOP Read Write ILLEGAL 2 Precharge ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) Term Burst --> Row Active Term Burst, start new Burst Read 3 Term Burst, start new Burst Write 3 ILLEGAL 2 Term Burst, execute Row Precharge ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) Term Burst --> Row Active Term Burst, start new Burst Read 3 Term Burst, start new Burst Write 3 ILLEGAL 2 Term Burst, execute Row Precharge 3 ILLEGAL NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) ILLEGAL 2 ILLEGAL 2 ILLEGAL ILLEGAL 2 ILLEGAL NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) ILLEGAL 2 ILLEGAL 2 ILLEGAL ILLEGAL 2 ILLEGAL Row Active Read Write Read with Auto Precharge Write with Auto Precharge 28/30 MSM56V16160F FUNCTION TRUTH TABLE (Table 1) (2/2) Current State Precharge 1 CS H L L L L L L H L L L L L L H L L L L L L H L L L L H L L L L RAS X H H H L L L X H H H L L L X H H H L L L X H H L L X H H H L CAS X H H L H H L X H H L H H L X H H L H H L X H L H L X H H L X WE X H L X H L X X H L X H L X X H L X H L X X X X X X X H L X X BA X X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X X X X X X X X X X ADDR X X X CA RA A10 X X X X CA RA A10 X X X X CA RA A10 X X X X X X X X X X X NOP --> Idle after tRP NOP --> Idle after tRP ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 NOP 4 ILLEGAL NOP NOP ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL Action Write Recovery Row Active NOP --> Row Active after tRCD NOP --> Row Active after tRCD ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL NOP --> Idle after tRC NOP --> Idle after tRC ILLEGAL ILLEGAL ILLEGAL NOP NOP ILLEGAL ILLEGAL ILLEGAL Refresh Mode Register Access ABBREVIATIONS RA = Row Address CA = Column Address BA = Bank Address AP = Auto Precharge NOP = No OPeration command *Notes : 1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs. 2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. Satisfy the timing of lCCD and tWR to prevent bus contention. 4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10. 5. Illegal if any bank is not idle. 29/30 MSM56V16160F FUNCTION TRUTH TABLE for CKE (Table 2) Current State (n) Self Refresh CKEn-1 H L L L L L L Power Down H L L L L L L All Banks Idle 6 (ABI) H H H H H H H H L Any State Other than Listed Above H H L L CKEn X H H H H H L X H H H H H L H L L L L L L L L H L H L CS X H L L L L X X H L L L L X X H L L L L L L X X X X X RAS X X H H H L X X X H H H L X X X H H H L L L X X X X X CAS X X H H L X X X X H H L X X X X H H L H L L X X X X X WE X X H L X X X X X H L X X X X X H L X L H L X X X X X ADDR X X X X X X X X X X X X X X X X X X X X X X X X X X X INVALID Exit Self Refresh --> ABI Exit Self Refresh --> ABI ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self Refresh) INVALID Exit Power Down --> ABI Exit Power Down --> ABI ILLEGAL ILLEGAL ILLEGAL 6 NOP (Continue power down mode) Refer to Table 1 Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh ILLEGAL NOP Refer to Operations in Table 1 Begin Clock Suspend Next Cycle Enable Clock of Next Cycle Continue Clock Suspension Action *Notes : 6. Power-down and self-refresh can be entered only when all the banks are in an idle state. 30/30 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit and assembly designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. OKI assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to:traffic control, automotive, safety, aerospace, nuclear power control, and medical, including lift support and maintenance. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. 2. 3. 4. 5. 6. 7. 8. Copyright 1997 OKI ELECTRIC INDUSTRY CO.,LTD. |
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